Design automation for integrated circuits (ICs), particularly application specific integrated circuits (ASICs) or entire digital systems on single chipsets, is becoming increasingly important as the integrated circuits (ICs) become more complex and dense. Design modeling, layout and verification of these integrated circuits (ICs), for example, are becoming more complex and time intensive. A broad range of design tools may be used to generate and analyze models of an intended system for design mistakes prior to fabrication. A typical tool suite may include behavioral languages and simulators (e.g., analog and digital simulators) used to model and simulate the operation of integrated circuits (ICs) or complete digital systems at many different levels of abstraction.
Behavioral languages may include Hardware Description Languages (HDLs) used to describe a piece of hardware for the purposes of simulation, modeling, testing, creation and documentation of designs. Popular Hardware Description Languages (HDLs) are Verilog and Very-High-Speed Integrated Circuit HDL (VHDL) developed for the Department of Defense and subsequently standardized by the Institute of Electrical & Electronics Engineering (IEEE). Other Hardware Description Languages include, but are not limited to, a Hardware Programming Language (AHPL), Computer Design Language (CDL), Consensus Language (CONLAN), Interactive Design Language (IDL), Instruction Set Processor Specification (ISPS), Test Generation and Simulation (TEGAS), Texas Instrument Hardware Description Language (TI-HDL), and Toshiba Description Language (TDL). However, such HDLs are typically not designed for verification. Therefore, a test bench that includes interfaced HDL programming, C or C++ programming, and various scripts, is typically required to simulate and verify the correctness of an HDL hardware model.
For complex chipset or digital system designs, VDHL simulations are preferred methods of verification of operational correctness and performance characteristics of complex integrated circuits or other electronic components or interface mechanisms in the chipset, such as Universal Serial Bus (USB) hubs for supporting multiple peripheral devices simultaneously, such as printers, scanners, digital cameras, modems, network adapters, tape drives, CD/DVD drives, hard disk drives and computer devices.
In many high speed digital signal interfaces such as USB interfaces of a chipset, the physical transmission medium consists of a wire (or bundle of wires), that is terminated on both ends with matched series or parallel termination resistance. The laws of physics dictate that a mis-match in termination resistance at the ends of the transmission line will result in an electrical reflection on the wire that occurs when a transmitted electrical signal is “bounced” off of the opposite end of a transmission cable from which it originated. This property may be used in some modern high-speed interfaces to recognize the presence (or lack of presence) of a peripheral device at the opposite end of a transmission cable.
In the past, analog simulators have been utilized to provide a continuous time function so as to evaluate the physical reflected wave response of the hardware model. However, evaluation at this level has been compute time intensive and impractical for VHDL functional validation. Digital simulators have also been used to model the reflected wave phenomenon. However, previous modeling of such a reflected wave phenomenon in a digital simulation has been limited to more obscure and intrusive methods of injecting simulation values directly into core logic.
Accordingly, there is a need for obtaining a more effective simulation of the properties of interest (the transmission line reflections) of a hardware model. In other words, there is a need for a method of representing the reflected wave phenomenon efficiently in a digital simulation for functional validation purposes.